Driver Pre - emphasis Signaling for On - Chip Global Interconnects

ZHANG, LIANG LEON. Driver Pre-emphasis Signaling for On-Chip Global Interconnects (Under the direction of Professor Paul D. Franzon). Signaling design for high performance VLSI systems has become an increasingly difficult task due to the delay/noise limitation for on-chip global interconnects. Repeater insertion techniques are widely used to improve the signal bandwidth of interconnect channels and to meet the delay goal of cross-chip communication, but even with a suboptimal delay approach, repeaters still consume a significant amount of power and area. They also increase the complexity of chip layout. As technologies continue to scale and operating frequencies continue to increase, the number of repeaters required increases exponentially. The intrinsic delay latency from repeaters themselves undermines total signal delay improvement. The techniques proposed to avoid or minimize repeaters, as well as the challenge of onchip global interconnects, are reviewed. A simplified delay design guideline is derived to determine whether inductive effects are important for the long on-chip interconnects used in this work (i.e. whether distributed RC or RLC model should be chosen). Equalization techniques are verified as a capable solution to replace repeater insertion in achieving lower latency and higher data throughput for on-chip communication. A circuit for driver pre-emphasis is proposed by combining equalization techniques with a traditional